In semiconductor integrated circuits (ICs) and, in particular, in static random access memories (SRAMs), data stored in a memory cell is read via a bit line pair and an input/output line pair. During a read operation, since a voltage difference across a bitline pair and a voltage difference across an input/output line pair are very small, a sense amplifier is used to sense small the differences in voltages.
In high-speed applications, sense amplifier based SRAMs require the sense amplifier have a reset capability. The resetting of the sense amplifier should happen with the 100% assurance of successful reading of sense data. Conventionally, it is maintained with the margin simulations across the functional process, voltage and temperatures (PVT) corners and margin PVT corners. Because there is no tracking of output data latched in an output latch, the conventional methods consume more time and subsequently, penalize a read/write cycle time, which results in a limitation in improving operation speed of a processor.